A conventional write driver for a semiconductor memory device writes data to a selected memory cell location whenever a write enable pulse is low. The write driver is subsequently disabled by the rising edge of the write enable pulse to end the write. It is important that the write driver is disabled before the next address becomes valid to prevent old data being written to the newly selected memory cell.
Address hold time is the period that the address has to stay valid after end of write. This parameter is determined by a race between the fastest selecting address path and the slowest path to end of write. End of write occurs when the bitlines are raised above the write level of the cells. If the next address is enabled too quickly, the data may be written to that address. Data hold time is the period that the user must hold data valid after end of write. If valid data ends too soon, invalid data will be written into the cell. Another write parameter is the write pulse width which is the minimum write enable pulse required to write data into a memory cell. This parameter determined by how fast the write enabling circuit connects the data input drivers to the internal data bus to write into memory. This parameter is also governed by how fast the write operation is stopped.
For a write operation ended using a write enable signal (e.g., Web) or other similar control signal, the control path is designed to achieve the required address hold time which delays the beginning of write. It is not possible to adjust beginning of write and end of write independently, and it is difficult to meet data hold time without the risk of writing to a wrong address.